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Xiaomi router freezes at boot after re-capping

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    Xiaomi router freezes at boot after re-capping

    I'm using Xiaomi Router 4A gigabit edition as wireless repeater. It worked fine for 2 years or so, but last week, wireless started to disappear.

    When I unplug/replug the power, it was working fine for a day/half a day or so until it freezes again.

    After testing with different power supply adapters and concluding it wasn't the issue I finally opened the case and this was the situation:



    Anyway I proceed to clean up the mess and replace all caps but unfortunately it made the situation worse. Now router can't even boot, either it freezes during kernel messages, or it boot-loops again during kernel boot.



    I'm very inexperienced not sure whether I f**d up something else on the board while soldering or where to start probing with multimeter etc. Any help is appreciated.

    Code:
    ===================================================================
            MT7621  stage1 code Oct 28 2018 20:39:32 (ASIC)
            CPU=500000000 HZ BUS=166666666 HZ
    ==================================================================
    Change MPLL source from XTAL to CR...
    do MEMPLL setting..
    MEMPLL Config : 0x11100000
    3PLL mode + External loopback
    === XTAL-40Mhz === DDR-1200Mhz ===
    PLL2 FB_DL: 0x10, 1/0 = 537/487 41000000
    PLL3 FB_DL: 0x15, 1/0 = 647/377 55000000
    PLL4 FB_DL: 0x16, 1/0 = 669/355 59000000
    do DDR setting..[01F40000]
    Apply DDR3 Setting...(use customer AC)
         0  8  16  24  32  40  48  56  64  72  80  88  96 104 112 120
       --------------------------------------------------------------------------------
    0000:|  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
    0001:|  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
    0002:|  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
    0003:|  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
    0004:|  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
    0005:|  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
    0006:|  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
    0007:|  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
    0008:|  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
    0009:|  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
    000A:|  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
    000B:|  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
    000C:|  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
    000D:|  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  1
    000E:|  0  0  0  0  0  0  0  0  0  1  1  1  1  1  1  1
    000F:|  0  0  0  0  1  1  1  1  1  1  1  1  1  1  0  0
    0010:|  1  1  1  1  1  1  1  1  1  0  0  0  0  0  0  0
    0011:|  1  1  1  1  0  0  0  0  0  0  0  0  0  0  0  0
    0012:|  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
    0013:|  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
    0014:|  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
    0015:|  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
    0016:|  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
    0017:|  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
    0018:|  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
    0019:|  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
    001A:|  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
    001B:|  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
    001C:|  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
    001D:|  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
    001E:|  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
    001F:|  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0  0
    DRAMC_DQSCTL1[0e0]=13000000
    DRAMC_DQSGCTL[124]=80000033
    rank 0 coarse = 15
    rank 0 fine = 72
    B:|  0  0  0  0  0  0  0  0  1  1  1  0  0  0  0  0
    opt_dle value:9
    DRAMC_DDR2CTL[07c]=C287221D
    DRAMC_PADCTL4[0e4]=000022B3
    DRAMC_DQIDLY1[210]=0C090909
    DRAMC_DQIDLY2[214]=06090907
    DRAMC_DQIDLY3[218]=0E09090A
    DRAMC_DQIDLY4[21c]=0B090C0A
    DRAMC_R0DELDLY[018]=00002221
    ==================================================================
            RX   DQS perbit delay software calibration 
    ==================================================================
    1.0-15 bit dq delay value
    ==================================================================
    bit|   0 1 2 3 4 5 6 7 8 9
    --------------------------------------
    0 |  9 9 9 11 7 9 8 6 7 7 
    10 |  9 11 8 9 8 8 
    --------------------------------------
    
    ==================================================================
    2.dqs window
    x=pass dqs delay value (min~max)center 
    y=0-7bit DQ of every group
    input delay:DQS0 =33 DQS1 = 34
    ==================================================================
    bit   DQS0   bit   DQS1
    0 (1~65)33 8 (1~61)31
    1 (1~65)33 9 (1~64)32
    2 (1~65)33 10 (2~66)34
    3 (1~64)32 11 (1~62)31
    4 (1~65)33 12 (1~64)32
    5 (1~65)33 13 (1~62)31
    6 (1~64)32 14 (1~66)33
    7 (1~66)33 15 (1~62)31
    ==================================================================
    3.dq delay value last
    ==================================================================
    bit|  0 1 2 3 4 5 6 7 8  9
    --------------------------------------
    0 |  9 9 9 12 7 9 9 6 10 9 
    10 |  9 14 10 12 9 11 
    ==================================================================
    ==================================================================
       TX perbyte calibration 
    ==================================================================
    DQS loop = 15, cmp_err_1 = ffff0000 
    dqs_perbyte_dly.last_dqsdly_pass[0]=15, finish count=1 
    dqs_perbyte_dly.last_dqsdly_pass[1]=15, finish count=2 
    DQ loop=15, cmp_err_1 = ffff0000
    dqs_perbyte_dly.last_dqdly_pass[0]=15, finish count=1 
    dqs_perbyte_dly.last_dqdly_pass[1]=15, finish count=2 
    byte:0, (DQS,DQ)=(8,8)
    byte:1, (DQS,DQ)=(8,8)
    DRAMC_DQODLY1[200]=88888888
    DRAMC_DQODLY2[204]=88888888
    20,data:88
    [EMI] DRAMC calibration passed
    
    ===================================================================
            MT7621  stage1 code done 
            CPU=500000000 HZ BUS=166666666 HZ
    ===================================================================
    
    
    U-Boot 1.1.3 (Aug 18 2020 - 11:10:29)
    
    Board: Ralink APSoC DRAM: 128 MB
    Power on memory test. Memory size= 128 MB...OK!
    relocate_code Pointer at: 87fb0000
    
    Config XHCI 40M PLL 
    RT2880_RSTSTAT_REG 0xc0030000
    ***************************
    Board power on Occurred
    ***************************
    flash manufacture id: ef, device id 40 18
    find flash: W25Q128BV
    ============================================ 
    Ralink UBoot Version: 5.0.0.0
    -------------------------------------------- 
    ASIC MT7621A DualCore (MAC to MT7530 Mode)
    DRAM_CONF_FROM: Auto-Detection 
    DRAM_TYPE: DDR3 
    DRAM bus: 16 bit
    Xtal Mode=3 OCP Ratio=1/3
    Flash component: SPI Flash
    Date:Aug 18 2020 Time:11:10:29
    ============================================ 
    icache: sets:256, ways:4, linesz:32 ,total:32768
    dcache: sets:256, ways:4, linesz:32 ,total:32768 
    
     ##### The CPU freq = 880 MHZ #### 
     estimate memory size =128 Mbytes
    #Reset_MT7530
    set LAN/WAN LLLLW
    
    restore_defaults:0
    
    Please choose the operation: 
      1: Load system code to SDRAM via TFTP. 
      2: Load system code then write to Flash via TFTP. 
      3: Boot system code via Flash (default).
      4: Entr boot command line interface.
      7: Load Boot Loader code then write to Flash via Serial. 
      9: Load Boot Loader code then write to Flash via TFTP. 
    
      n3: System Boot system code via Flash.
    Booting System 1
    Erasing SPI Flash...
    raspi_erase: offs:30000 len:10000
    .
    Writing to SPI Flash...
    .
    done
    ## Booting image at bc180000 ...
      Image Name:  MIPS OpenWrt Linux-3.10.14
      Image Type:  MIPS Linux Kernel Image (lzma compressed)
      Data Size:  1690519 Bytes = 1.6 MB
      Load Address: 81001000
      Entry Point: 81387e90
      Verifying Checksum ... OK
      Uncompressing Kernel Image ... OK
    Erasing SPI Flash...
    raspi_erase: offs:30000 len:10000
    .
    Writing to SPI Flash...
    .
    done
    commandline uart_en=1 factory_mode=0 mem=128m root=/dev/mtdblock9
    No initrd
    ## Transferring control to Linux (at address 81387e90) ...
    ## Giving linux memsize in MB, 128
    
    Starting kernel ...
    
    
    LINUX started...
    
     THIS IS ASIC
    
    SDK 5.0.S.0
    [  0.000000] Initializing cgroup subsys cpuset
    [  0.000000] Initializing cgroup subsys cpu
    [  0.000000] Linux version 3.10.14 (jenkins@327eefce2db8) (gcc version 4.8.5 (crosstool-NG crosstool-ng-1.22.0) ) #1 MiWiFi-R4A-3.0.24 SMP Tue Aug 18 11:17:57 UTC 2020
    [  0.000000] 
    [  0.000000] The CPU feqenuce set to 880 MHz
    [  0.000000] GCMP present
    [  0.000000] CPU0 revision is: 0001992f (MIPS 1004Kc)
    [  0.000000] Software DMA cache coherency
    [  0.000000] Determined physical RAM map:
    [  0.000000] memory: 08000000 @ 00000000 (usable)
    [  0.000000] User-defined physical RAM map:
    [  0.000000] memory: 08000000 @ 00000000 (usable)
    [  0.000000] Initrd not found or empty - disabling initrd
    [  0.000000] Zone ranges:
    [  0.000000]  DMA   [mem 0x00000000-0x00ffffff]
    [  0.000000]  Normal  [mem 0x01000000-0x07ffffff]
    [  0.000000] Movable zone start for each node
    [  0.000000] Early memory node ranges
    [  0.000000]  node  0: [mem 0x00000000-0x07ffffff]
    [  0.000000] Detected 3 available secondary CPU(s)
    [  0.000000] Primary instruction cache 32kB, 4-way, VIPT, linesize 32 bytes.
    [  0.000000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
    [  0.000000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
    [  0.000000] PERCPU: Embedded 7 pages/cpu @8160e000 s6912 r8192 d13568 u32768
    [  0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 32512
    [  0.000000] Kernel command line: console=ttyS1,115200n8 uart_en=1 factory_mode=0 mem=128m root=/dev/mtdblock9
    [  0.000000] drivers/mtd/mtdpart.c mtd_init_bootos 1085
    [  0.000000] PID hash table entries: 512 (order: -1, 2048 bytes)
    [  0.000000] Dentry cache hash table entries: 16384 (order: 4, 65536 bytes)
    [  0.000000] Inode-cache hash table entries: 8192 (order: 3, 32768 bytes)
    [  0.000000] Writing ErrCtl register=00068000
    [  0.000000] Readback ErrCtl register=00068000
    [  0.000000] allocated 262144 bytes of page_cgroup
    [  0.000000] please try 'cgroup_disable=memory' option if you don't want memory cgroups
    [  0.000000] Memory: 124392k/131072k available (3657k kernel code, 6680k reserved, 993k data, 272k init, 0k highmem)
    [  0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=4, Nodes=1
    [  0.000000] Hierarchical RCU implementation.
    [  0.000000] NR_IRQS:128
    [  0.000000] console [ttyS1] enabled
    [  0.150000] Calibrating delay loop... 577.53 BogoMIPS (lpj=2887680)
    [  0.210000] pid_max: default: 32768 minimum: 301
    [  0.210000] Mount-cache hash table entries: 512
    [  0.220000] Initializing cgroup subsys memory
    [  0.220000] launch: starting cpu1
    [  0.230000] launch: cpu1 gone!
    [  0.230000] CPU1 revision is: 0001992f (MIPS 1004Kc)
    [  0.230000] Primary instruction cache 32kB, 4-way, VIPT, linesize 32 bytes.
    [  0.230000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
    [  0.230000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
    [  0.290000] Synchronize counters for CPU 1: done.
    [  0.300000] launch: starting cpu2
    [  0.300000] launch: cpu2 gone!
    [  0.300000] CPU2 revision is: 0001992f (MIPS 1004Kc)
    [  0.300000] Primary instruction cache 32kB, 4-way, VIPT, linesize 32 bytes.
    [  0.300000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
    [  0.300000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
    [  0.360000] Synchronize counters for CPU 2: done.
    [  0.370000] launch: starting cpu3
    [  0.370000] launch: cpu3 gone!
    [  0.370000] CPU3 revision is: 0001992f (MIPS 1004Kc)
    [  0.370000] Primary instruction cache 32kB, 4-way, VIPT, linesize 32 bytes.
    [  0.370000] Primary data cache 32kB, 4-way, PIPT, no aliases, linesize 32 bytes
    [  0.370000] MIPS secondary cache 256kB, 8-way, linesize 32 bytes.
    [  0.430000] Synchronize counters for CPU 3: done.
    [  0.440000] Brought up 4 CPUs
    [  0.440000] devtmpfs: initialized
    [  0.450000] NET: Registered protocol family 16
    [  0.750000] release PCIe RST: RALINK_RSTCTRL = 7000000
    [  0.750000] PCIE PHY initialize
    [  0.750000] ***** Xtal 40MHz *****
    [  0.760000] start MT7621 PCIe register access
    
    [B]freezes around here though not sometimes it goes a little bit further[/B]
    Attached Files
    Last edited by hinisa; 07-08-2023, 06:13 AM.

    #2
    Re: Xiaomi router freezes at boot after re-capping

    "NOBBY" ??
    wtf is that?

    do it again - use panasonic FR or rubycon ZL or some other decent low esr caps
    and you added an extra cap not in the original picture - that may have been unwise unless you know what it connects with.

    Comment


      #3
      Re: Xiaomi router freezes at boot after re-capping

      Agree with stj, I would also clean the board because it looks like shit, electrolyte might have leaked on it and that is conductive...
      "The one who says it cannot be done should never interrupt the one who is doing it."

      Comment


        #4
        Re: Xiaomi router freezes at boot after re-capping

        Originally posted by stj View Post
        "NOBBY" ??
        wtf is that?

        do it again - use panasonic FR or rubycon ZL or some other decent low esr caps
        and you added an extra cap not in the original picture - that may have been unwise unless you know what it connects with.
        Unfortunately there's only 1 place in town who sells small caps and only this no-name crap.

        Extra cap is "cost optimization" by Xiaomi. It's populated in older revisisons

        I actually also have the older revision and I've checked before installing they're exactly same caps (kys 470uf 25v), only differ in quantity.

        Originally posted by Per Hansson View Post
        Agree with stj, I would also clean the board because it looks like shit, electrolyte might have leaked on it and that is conductive...
        Already cleaned in the 2nd pic.

        Comment


          #5
          Re: Xiaomi router freezes at boot after re-capping

          Originally posted by hinisa View Post
          Unfortunately there's only 1 place in town who sells small caps and only this no-name crap.

          I actually also have the older revision and I've checked before installing they're exactly same caps (kys 470uf 25v), only differ in quantity.
          The original small caps looks to be LOW ESR 105°C rated capacitors.
          Your replacement look to be general purpose 85°C capacitors.

          If you are unable to get better capacitors a test could be to stop the boot process and load a firmware image via TFTP server and see if the unit works.
          Because it is possible the firmware became corrupted when the caps got bad...
          "The one who says it cannot be done should never interrupt the one who is doing it."

          Comment


            #6
            Re: Xiaomi router freezes at boot after re-capping

            if that uses a 12v psu then you could possibly scavenge some 16v caps from an old motherboard.

            Comment


              #7
              Re: Xiaomi router freezes at boot after re-capping

              hmm

              "LE PET"!

              Comment


                #8
                Interesting, I got the same router but the first revision from 2019, bought early 2020. Been working 24/7 first as a router, then as dumb access point, flashed with openwrt. Rock stable, newer any problem with it.
                This is the second forum post with blown caps on the newer revision (there is one post also on openwrt forum).
                On newer revisions Xiaomi omitted shielding from the SOC and wifi chips and one of the larger caps on the input.
                Could it be that OP's router blew the caps because of one cap less on the input?
                I opened my router today, all caps are OK, no bulging, measured in place as 925 uF for larger input ones (470 uF, 25V) and the ESR of 0.08. The smaller caps are 470 uF 10V, measured 954uF and 0.12 ohm ESR. Both pairs are in parallel so the measurement is not accurate.
                Attached Files

                Comment


                  #9
                  I think that is not anymore problem capacitor and their quality, but previous leaking spillage under cristal, ic and small component... on many point you can see joint plague, and function of these is highly questionable, connections is unreliable or broken or partialy shorted due to stalled residue under its legs. It is realy no point to repair such condition, maybe is firmware corupte and so on...

                  It is good reminder that 24/7 router should hang on wall respect to capacitors

                  Comment

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