Understanding bus values
Hi all!
This time I won't be burdening you with questions of experience and so, but pure theory is on on the hand right now.
I have difficulties understanding the bandwidth speed of FSB and HT, Wikipedia is cloudy too, so that I want to point out (and be verified) certain things.
I'm worried about the real speed, meaning MegaTransfers per Second (MT/s). By my knowledge, I say FSB (as in PIII) is calculated like this, for instance:
FSB of 100MHz x 1 x 8 = 800MB/s
Where 100MHz is the clock of the bus, 1 is the cycle length (I guess it may be compared to burst mode in DRAM technologies), 8 is the 8bytes of a 64bit width of the bus. This is clear to me, let's move on with the core2 extreme:
FSB of 400MHz x 4 x 8 = 12800MB/s
The very same as above, only increased values. Now let's move to the problem. Problem with HyperTransport 1.0 (1.1) to be specific.
FSB of 200MHz x 4 x 2 = 1600MB/s
Yes I know all of the FSB should be base clock or BCLK, but here's the thing: 200 is the clock, 4 is the HT1.0 multiplier and 2 is the DDR ability of the HT. I'm using MBs deliberately as the market does (with AMD it did so) instead of MT/s, because right now I'm confused - where in that pattern is the bus bit-width value? Since the hypertransport has a 16bit connections, I should add one more ''x 2'' to it, thus getting the correct values, no?
Then it would be total fo 3200MB/s (or MT/s). Then why the advetisemens always shows 1600MTs or 2000MTs if the HT multiplier is 5, not 4000MTs?
Need to know if I'm correct, also just wondering if these results (3200 & 4000) are uni-directional or bi-directional.
This time I won't be burdening you with questions of experience and so, but pure theory is on on the hand right now.
I have difficulties understanding the bandwidth speed of FSB and HT, Wikipedia is cloudy too, so that I want to point out (and be verified) certain things.
I'm worried about the real speed, meaning MegaTransfers per Second (MT/s). By my knowledge, I say FSB (as in PIII) is calculated like this, for instance:
FSB of 100MHz x 1 x 8 = 800MB/s
Where 100MHz is the clock of the bus, 1 is the cycle length (I guess it may be compared to burst mode in DRAM technologies), 8 is the 8bytes of a 64bit width of the bus. This is clear to me, let's move on with the core2 extreme:
FSB of 400MHz x 4 x 8 = 12800MB/s
The very same as above, only increased values. Now let's move to the problem. Problem with HyperTransport 1.0 (1.1) to be specific.
FSB of 200MHz x 4 x 2 = 1600MB/s
Yes I know all of the FSB should be base clock or BCLK, but here's the thing: 200 is the clock, 4 is the HT1.0 multiplier and 2 is the DDR ability of the HT. I'm using MBs deliberately as the market does (with AMD it did so) instead of MT/s, because right now I'm confused - where in that pattern is the bus bit-width value? Since the hypertransport has a 16bit connections, I should add one more ''x 2'' to it, thus getting the correct values, no?
Then it would be total fo 3200MB/s (or MT/s). Then why the advetisemens always shows 1600MTs or 2000MTs if the HT multiplier is 5, not 4000MTs?
Need to know if I'm correct, also just wondering if these results (3200 & 4000) are uni-directional or bi-directional.
Comment