I have been trouble shooting a Toshiba 42hp83 Plasma TV for some weeks now. In searching the internet, I have only found two situations like mine, however no solutions and was hoping that maybe somebody has seen this type of issue or has some insight.
The plasma display, Y sustain, X sustain, and Y buffers are all Samsung brand.
My TV starts up fine with a good picture and after some 10 or 20 seconds, the picture will start to degrade (what I call pixelate) to a picture with a line going through the middle of the screen, from left to right with the rest of the screen black or pretty much black. The picture degrades by the pixels turning black or hanging on a specific color then going black. This does not happen all at once, but rather over a period of several seconds.
When the TV was assembled ( I have it disassembled for repair now), the picture would come back after 15 or 20 minutes, after which I could watch a whole movie with the screen holding good. In its disassembled state, I have not had the picture come back, although I have rarely ran it for 15+ minutes…
I have included pictures of the TV at the start, starting to degraded, then degraded. Note that my shutter speed is pretty slow, and I tried to minimize the reflection on the display panel...taking a good picture of a display was a little more challenging then I had thought…the first picture may not show it completely, but that is a good picture. Images are displayed/numbered in the order taken.
The sound is good, the display always turns on and stays on (that is, it does not shut itself down with any of the red blinking LED issues that other posts talk about).
I have a repair manual with instructions on how to put the display in a “Full White/Slick Raster” mode. In this mode, the display will last much longer versus when trying to display a moving image from a movie. In the full white mode, the display can last 5 to 10 minutes before it degrades
I checked all the main voltages, and slightly adjusted them (no voltage was originally more then 1.8 volts out with Va and Vsc being less then 0.5 volt out . The voltages are steady whether the picture is good or bad. Checked in Full White mode)
Va == specified at 70 volts, set to and measured at 70 volts
Vsc == specified at -60 volts, set to and measured at -60 volts
Vs == specified at 170 volts, set to and measured at 170 volts
Ve == specified at 150 volts, set to and measured at 150 volts
Vset == specified at 160 volts, set to and measured at 160 volts
In the service manual, there is a procedure for Y-Main circuit board adjustments to perform when replacing the Y main with a new Y main board. Believing that the Y main board was at fault, and prior to ordering the new board, I wanted to verify that I could actually measure these signals and locate the proper adjustments. I have attached the expected waveform as shown in the repair manual.
What I found in doing this, is that when the picture is good, the measured signal matches the signal as described in the manual. When the picture is bad, the signal I measure does not match the manual, it is clipped. In fact, as the picture starts to degrade, you can see this signal toggle between good and clipped prior to remaining at the clipped state.
Y Main board adjustment figure, as specified in the manual page 70. (click on image below to zoom in)
Figure 1 File name 104_Yrr_gd_pic_42hp83_186_8689.JPG, Good picture, YRR measure from logic board
Channel C: Logic board signal (low voltage)
Channel A: Y buffer signal ( High voltage)
Channel B: Yrr control signal from logic board (low voltage)
Figure 2 File name 204_Yrr_bd_pic_42hp83_186_8689.JPG, Bad picture, YRR measure from logic board
When the picture is bad, the signal does not contain the upper portion of the signal (appears clipped).
In researching this issue on the internet, I came across another manual for Samsung display boards that showed this Y Main signal with a description of the control signals for it. It showed that the Yrr signal was responsible for the ramp up portion of the signal and that the Yfr (not shown) was also noted to be responsible for the down slope of the signal.
Additional Items I checked:
1) There are a total of 17 logic signals that go from the logic board to the Y main board (that I could identify). I measured each of these with good picture and after bad picture against the y-main board adjustment signal as described above. These signals are consistently the same no matter good or bad picture.
2) There are a total of 5 logic signals that go from the logic board to the X main board (that I could identify). I measured each of these with good picture and after bad picture against the y-main board adjustment signal as described above. These signals are consistently the same no matter good or bad picture.
3) For the Yrr and Yfr, I verified the voltage output levels at the logic board against the input buffer (mm74hct) specifications that these feed into on the Y-Main board. I did not see any issues. My thought being that maybe the signals have become borderline and are not high enough in voltage to faithfully trigger the proper pulse.
4) Additionally I have gone onto the Y main board itself and making measurements at the adjustment area of VR5002 (Yrr is referenced on the PCB), I have found that FET Q5010, and IC U5014 are part of this circuit that generates the Y main pulse. This makes sense as written on the board there is also a reference to Yrr. I have been able measure the input to IC U5014 which is a driver to Q5010. The inputs to U5014, via R5139 and R5140, are consistent between good picture and bad picture. The signal input via R5139 is consistent with Yrr. However, with an ohm meter, I have not been able to trace it directly back to Yrr at the input ribbon cable connector. I am assuming there are several buffer circuits in between. At Q5010, the signal measured there is of the same shape as the signal for Y main adjustment. The signal at Q5010 also appears clipped during bad picture. As checked with my ohm meter, Q5010 is not directly connected to the Y buffer boards, there must be some additional circuitry in between.
The following is a plot of the N channel FET Q5010 when picture is good. Measurements taken at the leads of Q5010
Channel A is the gate,
Channel B is the Drain
Channel D is the Source.
The following is a plot of Q5010 when picture is Bad.
Channel A is the gate,
Channel B is the Drain
Channel D is the Source.
The voltage on the Drain is dropping out while the voltage on the Gate and source is “clipped”.
Not having the schematic, It is difficult to understand where the voltage is coming from (or in this case not coming from) that is causing the problem.
5) As a last resort, with a bad picture being displayed, I disconnected each of the Y buffers while leaving the other one connected (powering the set off prior and powering back on after disconnecting), the Y main signal was still clipped. I had expected that if one of the Y buffers were causing this problem, that the Y main signal would recover, it did not, it remained the same. Additionally, the whole screen remained dark, I had hoped if a problem Y buffer was removed, then half the screen would display.
In thinking the Y main board was at fault, I replaced it. I have also replaced the X main board. The display operates as before, however the good picture will last longer (upwards of a minute) before degrading. Sometimes it will start to degrade and pop back to good before starting to degrade again.
My thoughts take me to the Logic board as the problem, while I am able to measure signals between good picture and bad picture, I am not able to know if the noise levels on the signals are appropriate, or if the timing between logic board signals remains consistent between good picture and bad picture.
There is also one last measurement I made that I don't understand. When I removed both Y buffer boards from the plasma panel, I again measure the Y main board timing signal at Q5010, I expected to see either a good signal or clipped signal, what I saw was neither, the signal was corrupted.
I am wondering if the plasma panel itself has gone bad. Is there a specific voltage pulse coming from one of the many other buffers that inter plays with this Y main board timing signal, therefore when I disconnected the Y buffers from the Y main board, the Y main board is not able to complete the signal because it is missing the signal from the plasma display? Would this mean that the plasma panel itself is failing?
Would anybody have board level schematics for the Y main board and Y buffer boards?
Thoughts?
Sorry for the long post, I have been working on this for some time and wanted to also share some detail.
Thanks.
The plasma display, Y sustain, X sustain, and Y buffers are all Samsung brand.
My TV starts up fine with a good picture and after some 10 or 20 seconds, the picture will start to degrade (what I call pixelate) to a picture with a line going through the middle of the screen, from left to right with the rest of the screen black or pretty much black. The picture degrades by the pixels turning black or hanging on a specific color then going black. This does not happen all at once, but rather over a period of several seconds.
When the TV was assembled ( I have it disassembled for repair now), the picture would come back after 15 or 20 minutes, after which I could watch a whole movie with the screen holding good. In its disassembled state, I have not had the picture come back, although I have rarely ran it for 15+ minutes…
I have included pictures of the TV at the start, starting to degraded, then degraded. Note that my shutter speed is pretty slow, and I tried to minimize the reflection on the display panel...taking a good picture of a display was a little more challenging then I had thought…the first picture may not show it completely, but that is a good picture. Images are displayed/numbered in the order taken.
The sound is good, the display always turns on and stays on (that is, it does not shut itself down with any of the red blinking LED issues that other posts talk about).
I have a repair manual with instructions on how to put the display in a “Full White/Slick Raster” mode. In this mode, the display will last much longer versus when trying to display a moving image from a movie. In the full white mode, the display can last 5 to 10 minutes before it degrades
I checked all the main voltages, and slightly adjusted them (no voltage was originally more then 1.8 volts out with Va and Vsc being less then 0.5 volt out . The voltages are steady whether the picture is good or bad. Checked in Full White mode)
Va == specified at 70 volts, set to and measured at 70 volts
Vsc == specified at -60 volts, set to and measured at -60 volts
Vs == specified at 170 volts, set to and measured at 170 volts
Ve == specified at 150 volts, set to and measured at 150 volts
Vset == specified at 160 volts, set to and measured at 160 volts
In the service manual, there is a procedure for Y-Main circuit board adjustments to perform when replacing the Y main with a new Y main board. Believing that the Y main board was at fault, and prior to ordering the new board, I wanted to verify that I could actually measure these signals and locate the proper adjustments. I have attached the expected waveform as shown in the repair manual.
What I found in doing this, is that when the picture is good, the measured signal matches the signal as described in the manual. When the picture is bad, the signal I measure does not match the manual, it is clipped. In fact, as the picture starts to degrade, you can see this signal toggle between good and clipped prior to remaining at the clipped state.
Y Main board adjustment figure, as specified in the manual page 70. (click on image below to zoom in)
Figure 1 File name 104_Yrr_gd_pic_42hp83_186_8689.JPG, Good picture, YRR measure from logic board
Channel C: Logic board signal (low voltage)
Channel A: Y buffer signal ( High voltage)
Channel B: Yrr control signal from logic board (low voltage)
Figure 2 File name 204_Yrr_bd_pic_42hp83_186_8689.JPG, Bad picture, YRR measure from logic board
When the picture is bad, the signal does not contain the upper portion of the signal (appears clipped).
In researching this issue on the internet, I came across another manual for Samsung display boards that showed this Y Main signal with a description of the control signals for it. It showed that the Yrr signal was responsible for the ramp up portion of the signal and that the Yfr (not shown) was also noted to be responsible for the down slope of the signal.
Additional Items I checked:
1) There are a total of 17 logic signals that go from the logic board to the Y main board (that I could identify). I measured each of these with good picture and after bad picture against the y-main board adjustment signal as described above. These signals are consistently the same no matter good or bad picture.
2) There are a total of 5 logic signals that go from the logic board to the X main board (that I could identify). I measured each of these with good picture and after bad picture against the y-main board adjustment signal as described above. These signals are consistently the same no matter good or bad picture.
3) For the Yrr and Yfr, I verified the voltage output levels at the logic board against the input buffer (mm74hct) specifications that these feed into on the Y-Main board. I did not see any issues. My thought being that maybe the signals have become borderline and are not high enough in voltage to faithfully trigger the proper pulse.
4) Additionally I have gone onto the Y main board itself and making measurements at the adjustment area of VR5002 (Yrr is referenced on the PCB), I have found that FET Q5010, and IC U5014 are part of this circuit that generates the Y main pulse. This makes sense as written on the board there is also a reference to Yrr. I have been able measure the input to IC U5014 which is a driver to Q5010. The inputs to U5014, via R5139 and R5140, are consistent between good picture and bad picture. The signal input via R5139 is consistent with Yrr. However, with an ohm meter, I have not been able to trace it directly back to Yrr at the input ribbon cable connector. I am assuming there are several buffer circuits in between. At Q5010, the signal measured there is of the same shape as the signal for Y main adjustment. The signal at Q5010 also appears clipped during bad picture. As checked with my ohm meter, Q5010 is not directly connected to the Y buffer boards, there must be some additional circuitry in between.
The following is a plot of the N channel FET Q5010 when picture is good. Measurements taken at the leads of Q5010
Channel A is the gate,
Channel B is the Drain
Channel D is the Source.
The following is a plot of Q5010 when picture is Bad.
Channel A is the gate,
Channel B is the Drain
Channel D is the Source.
The voltage on the Drain is dropping out while the voltage on the Gate and source is “clipped”.
Not having the schematic, It is difficult to understand where the voltage is coming from (or in this case not coming from) that is causing the problem.
5) As a last resort, with a bad picture being displayed, I disconnected each of the Y buffers while leaving the other one connected (powering the set off prior and powering back on after disconnecting), the Y main signal was still clipped. I had expected that if one of the Y buffers were causing this problem, that the Y main signal would recover, it did not, it remained the same. Additionally, the whole screen remained dark, I had hoped if a problem Y buffer was removed, then half the screen would display.
In thinking the Y main board was at fault, I replaced it. I have also replaced the X main board. The display operates as before, however the good picture will last longer (upwards of a minute) before degrading. Sometimes it will start to degrade and pop back to good before starting to degrade again.
My thoughts take me to the Logic board as the problem, while I am able to measure signals between good picture and bad picture, I am not able to know if the noise levels on the signals are appropriate, or if the timing between logic board signals remains consistent between good picture and bad picture.
There is also one last measurement I made that I don't understand. When I removed both Y buffer boards from the plasma panel, I again measure the Y main board timing signal at Q5010, I expected to see either a good signal or clipped signal, what I saw was neither, the signal was corrupted.
I am wondering if the plasma panel itself has gone bad. Is there a specific voltage pulse coming from one of the many other buffers that inter plays with this Y main board timing signal, therefore when I disconnected the Y buffers from the Y main board, the Y main board is not able to complete the signal because it is missing the signal from the plasma display? Would this mean that the plasma panel itself is failing?
Would anybody have board level schematics for the Y main board and Y buffer boards?
Thoughts?
Sorry for the long post, I have been working on this for some time and wanted to also share some detail.
Thanks.
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