eeprom MEc16xx

[cgtec]

C.1 EEPROM (LOCATION 0X303FC)
The SFPU uses the EEPROM as the last 1K block (MEC161x / MEC162x) or 2K block
(MEC163x MEC164x / MEC165x) of flash memory space. Any flash binary programmed
to the flash must have 0xFFFFFFFF at location 0x303FC if the binary is
0x303FC or larger.
Please see Section 14.6.2.4 in the MEC161x / MEC162x PCS documentation or Section
16.6.1.1 in the MEC163x PCS documentation.
C.2 BOOT ROM CONTROL FLAGS (LOCATION 0XFFC)
Developers should be aware that setting Boot ROM Control Flag bits at location 0xFFC
in flash memory can have a drastic effect on the operation of the chip. Please take care
that the bits have the desired values when creating a binary image to be programmed
to flash memory.
The DWORD at address 00_0FFCh in the Flash Memory Array contains Boot ROM
Control Flags, which are loaded by hardware into the read-only Embedded Flash Initialization
Register following a VTR POR. The Boot ROM reads the state of the Control
Flags using the Embedded Flash Initialization Register. The Control Flags are defined
in Table C-1:.
The initial values of these bits out of the factory are all 1's (0xFF). The power-on
sequence of the board is determined by the timeout bits.

[earthoo7]

Re: eeprom MEc16xx

C.1 EEPROM (LOCATION 0X303FC)
The SFPU uses the EEPROM as the last 1K block (MEC161x / MEC162x) or 2K block
(MEC163x MEC164x / MEC165x) of flash memory space. Any flash binary programmed
to the flash must have 0xFFFFFFFF at location 0x303FC if the binary is
0x303FC or larger.
Please see Section 14.6.2.4 in the MEC161x / MEC162x PCS documentation or Section
16.6.1.1 in the MEC163x PCS documentation.
C.2 BOOT ROM CONTROL FLAGS (LOCATION 0XFFC)
Developers should be aware that setting Boot ROM Control Flag bits at location 0xFFC
in flash memory can have a drastic effect on the operation of the chip. Please take care
that the bits have the desired values when creating a binary image to be programmed
to flash memory.
The DWORD at address 00_0FFCh in the Flash Memory Array contains Boot ROM
Control Flags, which are loaded by hardware into the read-only Embedded Flash Initialization
Register following a VTR POR. The Boot ROM reads the state of the Control
Flags using the Embedded Flash Initialization Register. The Control Flags are defined
in Table C-1:.
The initial values of these bits out of the factory are all 1's (0xFF). The power-on
sequence of the board is determined by the timeout bits.

@cgtec
do u have SFPU V5.26 Document .pdf
if you have please upload.
thankyou