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A2179 820-01958 power up sequence: PMU_PVDDMAIN_EN always 0

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    A2179 820-01958 power up sequence: PMU_PVDDMAIN_EN always 0

    Dear all,

    I'm trying to fix an Apple A2179 (820-01958).

    The laptop had water poured over it while it was on. The audio board was corroded. The VBUS pins on the connector were completely eaten away. The main board shows no signs of corrosion, but most likely was also exposed to water. Also the water corrosion on the audio board might have led to damage on the main board.

    I tried first to check all pins coming from the audio board to the main board using the component tester of a Hameg HM303-6 to see if there is any damage. All looks fine. I see protection diodes.

    I disconnected the main board from everything except the battery. I plugged in a USB-C charger which activates the main boards power sequence.

    In the power up sequence I see that form PP1V8_SLPS2R on, the voltages pulse. PP1V8_SLPS2R is on for approx. 4s off for ~1s.
    PMU_PVDDMAIN_EN always stays below 0.001V. The component tester shows that PMU_PVDDMAIN_EN is partly actively driven to 0 by an output, partly driven by a pull-down. Triggering the HM303-6 on the PMU_PVDDMAIN_EN never shows any trigger.

    When voltages I see when supplies are on are the following:
    • PBUS (PPBUS_G3H) => ~ 11.3V
    • PP3V3_G3H_RTC 3.28V
    • PP3V3_G3H Varying, 3.22 to 2.29V depending on how much current is drawn.
    • PP1V8_SLPS2R 1.80V
    • PMU_CLK32K_SOC ⇒ Oscillating, freqeuncy matches approxiamtely
    • PP1V8_AWAKE 1.80V
    • PP1V8_SLPS2R_PMUGPIO 1.8029
    • PP1V1_SLPS2R 1.1026
    • PP0V8_SLPS2R 0.8012
    • PP0V82_SLPDDR 0.8227
    • PP3V3_AWAKE Varrying 3.22 to 3.26V
    • PPVDDCPUSRAM_AWAKE 0.8005
    • PP0V9_SLPDDR 0.8984
    • P1V1_SLPDDR_SOCFET_EN 1.8027
    • PP1V1_SLPDDR 1.1026
    • H9M 24MHz CLK ⇒ Oscillating, freqeuncy matches approxiamtely
    • PP1V2_AWAKE 1.211
    • PPVDDCPU_AWAKE 0.7555
    • PMU_SYS_ALIVE 1.7836
    • PMU_ACTIVE_READY 1.7977
    • PMU_COLD_RESET_L 1.79


    The power sequence diagram says as next: "H9M LOAD SECURE ROM, SMC BATTERY TRAP"

    I've checked the SoC ROM U4770. Data is being transferred on the MISO line. The transfer is complete seconds before all voltages break down and the power cycle restarts.

    I don't see any activity on the I2C bus to the battery. However, voltages seem fine.

    Checking the voltage drops along the GND I see the main consumer is the T2. The maximum voltage drop is ~50µV.

    This is where I'm stuck and don't know how to move further .

    I think the T2 is booting fine. I'm asking myself is what the battery trap should be and how to check that.

    Please help!
    Last edited by Unkraut; 01-30-2022, 11:12 AM.
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