How a plasma display panel (PDP) works

[jarapunga]

Re: How a plasma display panel (PDP) works

I noticed this thread while searching for a solution to a problem on an lg 42pt350 where both y-sus and z-sus boards had shorted igbits. I replaced the igbits but they all shorted again after the priming stage. I'm now on a quest as to why these same igbits have failed twice. Is it possible that I have a short inside the PDP module which is damaging these igbits?? According to Tom's article, the pdp module has an array of electrodes with gas in between. No chance for a short there?? Any opinions??

[Redjess]

Re: How a plasma display panel (PDP) works

I just happened to notice this thread. Interesting subject as when I tried for my first time to repair my LG 60PA6500, and just about had it fixed until I had a rookie blunder and ran it to check for power going to the lower address buffers without the metal cover, (I thought), cooked the ICs. Obviously it was a heat sink! I regret being a dumb ass often!

I think i did just that, ill start a thread about it. I am very much a rookie too.

[Redjess]

Re: How a plasma display panel (PDP) works

Thanks for that info, now on to digesting.

[kattyla]

Re: How a plasma display panel (PDP) works

Wooow det is awesome!!

[tom66]

Re: How a plasma display panel (PDP) works

Must be possible somehow but there's no documentation from Panasonic, I suspect that one of the processors will have an exposed debug port to which commands can be sent but where exactly would be a mystery. I know someone has had some luck accessing a VT50's debug port but they were not able to understand the options available.

[ReeceyBurger123]

Re: How a plasma display panel (PDP) works

To tweak the set you can do it in the service setting which will change how the controller drives the Panel. Tom will know exactly how to do that lol.

[12Bass]

Re: How a plasma display panel (PDP) works

Thanks, tom66, for the informative post! Up until OLED became commercially viable, plasma has been my favorite flat panel display technology. Nice to learn about how it works.

I have a 2012 UT50 Panasonic which I would like to tweak to improve the black levels, but there are no potentiometers for making such adjustments. Perhaps I should start a new thread?

[lookimback]

Re: How a plasma display panel (PDP) works

Awesome post! Now I have a question though. I encounter a lot of broken PDPs and I'd like to know why Samsung buffer boards are shorted 99% of the time, but Panasonic ones rarely ever are.

[tom66]

Re: How a plasma display panel (PDP) works

I just happened to notice this thread. Interesting subject as when I tried for my first time to repair my LG 60PA6500, and just about had it fixed until I had a rookie blunder and ran it to check for power going to the lower address buffers without the metal cover, (I thought), cooked the ICs. Obviously it was a heat sink! I regret being a dumb ass often!
My question is, would running a PDP on lower power settings in the picture quality menu help a PDP live longer? I usually run it on a medium setting and the panel is barely warm. On a high quality setting it gets toasty.
BTW Tom, many thanks again on your advice last year!

Yep, definitely it would help. The lifespan of the panel, and of the electronics, would be improved under lower brightness settings, especially so with modern panels where energy use varies wildly across brightness levels. (Older panels vary less.)

[Poor Flick]

Re: How a plasma display panel (PDP) works

A similar mechanism called ion implantation can happen.

The PDP experiences very high energy discharges within the cell, which causes damage to the MgO structure of the cell. This damage must be compensated by adjusting the drive waveform as the panel ages, generally requiring a higher priming energy.

Manufacturers sometimes get this wrong, a good example being the LG PC1D series where the priming algorithm appears to overcompensate leading to sparkling pixels across the panel.

Pioneer's KURO 9G also has a minor issue with degradation, but it can be compensated for by adjusting the voltages for older panels. Mine has 15,000 hours, and the only issue is a small amount of red mist at the bottom of the panel on pitch black scenes. I could probably get rid of that but it's not visible on anything but pitch black images so it doesn't really bother me.

I just happened to notice this thread. Interesting subject as when I tried for my first time to repair my LG 60PA6500, and just about had it fixed until I had a rookie blunder and ran it to check for power going to the lower address buffers without the metal cover, (I thought), cooked the ICs. Obviously it was a heat sink! I regret being a dumb ass often!
My question is, would running a PDP on lower power settings in the picture quality menu help a PDP live longer? I usually run it on a medium setting and the panel is barely warm. On a high quality setting it gets toasty.
BTW Tom, many thanks again on your advice last year!

[tom66]

Re: How a plasma display panel (PDP) works

Tom,
Very nice treatise on PDP and driver.

I always thought of PDP as millions of fluorescent tubes on end. I think about ways these can fail (kind of a pessimist, I suppose) and envision how lighting tubes turn black at the ends. This increases load on the ballasts which not only will be the failure of the tube but soon, the end for the ballasts.

Is this in any way analogous to PDPs? Or does such carbonization not happen in the PDP cells?

Thanks again for sharing your knowledge.

Cheers.

A similar mechanism called ion implantation can happen.

The PDP experiences very high energy discharges within the cell, which causes damage to the MgO structure of the cell. This damage must be compensated by adjusting the drive waveform as the panel ages, generally requiring a higher priming energy.

Manufacturers sometimes get this wrong, a good example being the LG PC1D series where the priming algorithm appears to overcompensate leading to sparkling pixels across the panel.

Pioneer's KURO 9G also has a minor issue with degradation, but it can be compensated for by adjusting the voltages for older panels. Mine has 15,000 hours, and the only issue is a small amount of red mist at the bottom of the panel on pitch black scenes. I could probably get rid of that but it's not visible on anything but pitch black images so it doesn't really bother me.

[jojo88]

Re: How a plasma display panel (PDP) works

Tom,
Very nice treatise on PDP and driver.

I always thought of PDP as millions of fluorescent tubes on end. I think about ways these can fail (kind of a pessimist, I suppose) and envision how lighting tubes turn black at the ends. This increases load on the ballasts which not only will be the failure of the tube but soon, the end for the ballasts.

Is this in any way analogous to PDPs? Or does such carbonization not happen in the PDP cells?

Thanks again for sharing your knowledge.

Cheers.

[xplayerx]

Re: How a plasma display panel (PDP) works

I Can Only Say WOW

[xplayerx]

Re: How a plasma display panel (PDP) works

I can Say Only Wow

[videobruce]

Re: How a plasma display panel (PDP) works

A cut & paste to a document for me.
Much thanks.

[jusjackin]

Re: How a plasma display panel (PDP) works

Thanks for this thread guys.

[tom66]

Re: How a plasma display panel (PDP) works

Line bleed is caused by finite nonzero resistance of the scan driver ICs and panel electrodes. Fundamental limitation of plasmas. You can get it with LCDs too on certain very high contrast images or with certain patterns.

The scan drivers are shift registers, have nothing to do with the image though, they just select which line to load one after another.

SEL = choose even/odd line
SIU = serial data input
OC1 = enable set 1
OC2 = enable set 2
CLK = serial data clock
(just guesses)

Glad you have a "spare" TV lying around. the SUS do not need isolation, the SCAN do, for the PASS-FET output (this blocks SUS from shorting the ramp waveforms which would be destructive.)

Perhaps try replicating as much of the SC board as possible (full schem available for U30, I think) then try changing it for your preferences.

DS1102D doesn't have a phosphor display so is pushing the capabilities of such an instrument.

[JackMiles]

Re: How a plasma display panel (PDP) works

By the way, Tom, do you know the source of panasonic line bleeding and flicker problem?
Line bleeding is a current leak in panel itself, IGBT scheme or image processing itself?

[JackMiles]

Re: How a plasma display panel (PDP) works

It's an ambitious project, I'll give you that.

The subfields are basically just same brightness levels but displayed for a longer period of time, so for example a subfield of length 1 might be about 1% as bright as one which is displayed 100 times over, each sustain event emits about the same light.

The line selection is logic level from control board, ground referenced. At the buffers, it is VFG referenced, that is the sustain node (without the Vsc applied.) This requires optoisolation.

Driving IGBTs at the required rate (around 200kHz) is a high level power electronics project. I would not be surprised if the first few boards work for some small amount of time before catastrophically failing. For learning experience, I would try experimenting with a different panel... maybe one not so valuable

A common sustain driver (SS) is a lot less ambitious than the addressed sustain driver.

Scope: minimum 100MHz digital scope like Rigol DS1074Z, DS2072A, Agilent 2000X, etc. You need the high waveform update rate to see the most detail.

"Depending on the display technology, the fields will be in binary lengths (512, 256, 128, 64, 32, 16, 8, 4, 2, 1) which allows any cell to be varied from zero intensity to 1023 intensity (arbitrary figures.)" - that means that they all differs only by quantyty of sustain impulses and displayed one after another, so, if i need "3" i set "1" for cell when "1 impulse", set "1" for cell when its "2 impulses" and set "0" for all others?

In VT60 manual theres SEL SIU OC1 OC2 and CLK signals for scanline selection. Any idea about them?

Well, i'll try first to "emulate" real oscilloscope for sus/select and hope my panel will live long enough. I hope)) For experiments will use old 42u30.
For driving IGBT on SUS and SCAN boards, do i need any optoisolation, or buffers already on board are enough?

Any idea about X-board lvds ?

Is Rigol DS1102D is ok ?

Thank you.

[tom66]

Re: How a plasma display panel (PDP) works

Hello Tom66.
In short time i'm planning to build my own pdp panel driver and really i'm out of knowledge. (very dissapointed about panasonic vt60, theres huge mistakes they didnt want to fix) The problem is: sub-fields and scan line+data line selection.
1)I don't ungerstand sub-fields at all) are dispaying subfield with "brighness 1" and then with "brightness 3" gives a brightness 4? How dithering works? Whats the order of subfields? One per line, all lines and again, or all per line and then next line?
2)About line selection: as i see it uses standart signals for making sustain/scan signals, but line selection and data lines for X board are lvds. What format, clock and how many bits it uses?
What oscillograph freq do i need to watch all signals in pdp, 100mhz is enough?
I'm very sorry for my bad english, but please help me if it is possible.

It's an ambitious project, I'll give you that.

The subfields are basically just same brightness levels but displayed for a longer period of time, so for example a subfield of length 1 might be about 1% as bright as one which is displayed 100 times over, each sustain event emits about the same light.

The line selection is logic level from control board, ground referenced. At the buffers, it is VFG referenced, that is the sustain node (without the Vsc applied.) This requires optoisolation.

Driving IGBTs at the required rate (around 200kHz) is a high level power electronics project. I would not be surprised if the first few boards work for some small amount of time before catastrophically failing. For learning experience, I would try experimenting with a different panel... maybe one not so valuable

A common sustain driver (SS) is a lot less ambitious than the addressed sustain driver.

Scope: minimum 100MHz digital scope like Rigol DS1074Z, DS2072A, Agilent 2000X, etc. You need the high waveform update rate to see the most detail.