Hi all, I'm working on an an A2289 which had a previous spill that was repaired. Now upon turning on the only signs of life are the trackpad and fans spinning. I succesfully performed a DFU restore, but after completion it did not boot into recovery mode and display still is not turning on (It didnt turn on during the DFU restore, as I believe you would expect to see the apple logo at some point?).
I have removed the logic board as well as the usb-c charging port and plugged the charger in and taken the following readings, which show that ALL_SYS_PWRGD is low at 1.78V. I took measurements of all the rails up to that, per the 'Power Sequence' page of the attached schematic (Boardview also attached). Any help would be greatly appreciated, as I currently take the remaining measurements in the sequence
I have removed the logic board as well as the usb-c charging port and plugged the charger in and taken the following readings, which show that ALL_SYS_PWRGD is low at 1.78V. I took measurements of all the rails up to that, per the 'Power Sequence' page of the attached schematic (Boardview also attached). Any help would be greatly appreciated, as I currently take the remaining measurements in the sequence
| PPDCIN_G3H | 19.9 |
| PP3V3_G3H | 3.28 |
| PPVCC_S0_CPU | 0.8 |
| PPVCCGT_S0_CPU | 0 |
| PPVCCSA_S0_CPU | 1.01 |
| PPVCCIO_S0_CPU | 0.94 |
| PPVCCEDRAM_S0_CPU | 0 |
| PP1V_S0SW | 1.04 |
| PP1V2_S0SW | 1.18 |
| PP1V_S3 | 1.03 |
| PP1V_PRIM | 1.04 |
| PPVPCORE_S5 | 1.03 |
| PP3V_G3H_RTC | 2.97 |
| ALL_SYS_PWRGD | 1.78 |
| PCH_RTC_RESET_L | 2.98 |
| PM_PCH_PWROK | 3.27 |
| PM_PCH_SYS_PWROK | 3.27 |
| PM_RSMRST_L | 3.27 |
| PM_SLP_S3_L | 3.27 |
| PM_SLP_S0_L | |
| PLT_RST_L | |
| PM_THRMTRIP_L | |
| PCH_PWRBTN_L | |
| CPU_PROCHOT_R_L | |
| CPU_CATERR_L | |
| CPU_VR_READY | |
| PMU_PVDDMAIN_EN | |
| UPC_PMU_RESET | |
| PP3V3_G3H_RTC | 3.27 |
| CHGR_EN_MVR | |
| P3V3G3S_EN | 1.78 |
| PP3V3_G3S | 3.27 |
| P1V8G3S_EN | 1.78 |
| PP1V8_IO_SSD0 | |
| PPVCCQ_ANI_SSD0 | |
| PP0V9_SSD0 | |
| PP2V5_NAND_SSD0 | |
| SSD0_WP_L | |
| SSD0_OCARINA_PFN_L | |
| SSD0_OCARINA_RESET_L | |
| SSD_PMU_RESET_L | |
| PP3V3_AWAKE | 3.27 |
| PMU_COLD_RESET_L | |
| PM_SLP_S4_L | |
| PM_SLP_S5_L | |
| TP_SMC_FIXTURE_MODE_L | |
| PP1V8_SLPS2R | 1.78 |
| SOC_SOCHOT_L | |
| PP1V2_AWAKE | 1.19 |
| PP0V82_SLPDDR | 0.81 |
| PPVDDCPU_AWAKE | 0.91 |
| PP1V8_S5 | 1.78 |
| PPBUS_G3H | 12.5 |
| PP1V8_G3S | |
| PMU_ACTIVE_READY | |
| PP3V3_S5 | |
| PVCCIO_EN | |
| CPU_C10_GATE_L | |
| PP0V9_SLPDDR | |
| PP1V1_SLPDDR | |
| PP1V1_SLPS2R | |
| PP1V8_AWAKE | 1.78 |
| PP1V8_SLPS2R_PMUVDDGPIO | |
| P1V1_SLPDDR_SOCFET_EN | |
| PMU_CLK32K_WLANBT | |
| SOC_WDOG | |
| PMU_CLK32K_SOC | |
| PMU_SYS_ALIVE | |
| P5VG3S_EN | |
| PP0V8_SLPS2R | |
| PPVDDCPUSRAM_AWAKE | 0.79 |
| P5VG3S_PGOOD | |
| PM_SYSRST_L | |
| SMC_SYSRST_L | |
| PP5V_G3S | 5.08 |
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