Hope someone can help.
Kinda confused about the power delivery of this unit. Instead of the normal 20V,, being delivered, only 5V is delivered to ADIN_1 in JP8, where the USB port board NS-A901 is connected. I used a USBC Tested connected in series, FYI.
Can someone explain how 20V or 5V is negotiated, and in this case, what circuit decides that? I was initially looking at PU3 (PMIC) but can't really understand where power is negotiated. Then looked at the SIO chip, however, how can the SIO chip negotiate if +3VALW_EC is not present. And saw that +3V_ALW is then produced by the the PU3 chip.
The USB3 DCIN board, the PU3, is quite an expensive gamble if replaced, while I have no idea how to program the SIO chip or even the thought of programming it is correct, given that the +3v power is non-existent.
I would really appreciate if someone could explain thoroughly.
Thanks!
MOD Edit: Link to schematic - https://www.badcaps.net/forum/showthread.php?t=81087
.
Kinda confused about the power delivery of this unit. Instead of the normal 20V,, being delivered, only 5V is delivered to ADIN_1 in JP8, where the USB port board NS-A901 is connected. I used a USBC Tested connected in series, FYI.
Can someone explain how 20V or 5V is negotiated, and in this case, what circuit decides that? I was initially looking at PU3 (PMIC) but can't really understand where power is negotiated. Then looked at the SIO chip, however, how can the SIO chip negotiate if +3VALW_EC is not present. And saw that +3V_ALW is then produced by the the PU3 chip.
The USB3 DCIN board, the PU3, is quite an expensive gamble if replaced, while I have no idea how to program the SIO chip or even the thought of programming it is correct, given that the +3v power is non-existent.
I would really appreciate if someone could explain thoroughly.
Thanks!
MOD Edit: Link to schematic - https://www.badcaps.net/forum/showthread.php?t=81087
.
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