Didn't realise this until looking at a modern (TX-P42U30B) SN board schematic.
Normally VFG is the SUS output, VSCN_F is the SUS+VSCN output. It follows SUS but ~150V higher for buffer ICs to select the right row in the addressing phase.
A lot of Panny boards have the equivalent of Q660, it connects VSCN_F to GND for the ramp down portion of the initialisation waveform. If this fails short, but the VFG is stuck HIGH (due to being at that part of the sustain waveform, for example...) this would reverse bias the buffer ICs with 200VDC!!! (As VFG would be at +200VDC, and VSCN_F would be at 0VDC, rather than VFG at +200VDC and VSCN_F at +350VDC.)
This would clearly cause fatal damage to the buffer ICs, AND since the energy path is from VSUS rather than VSCN_F there's a whole lot of energy to dump into the ICs...
As a bonus it would also probably damage the rest of the SC board, due to the pulse energy of discharging the VSCN capacitor...
I have not seen this circuit on modern LG/Samsung sustain boards... only Panasonic.
Just a thought/musing.
Normally VFG is the SUS output, VSCN_F is the SUS+VSCN output. It follows SUS but ~150V higher for buffer ICs to select the right row in the addressing phase.
A lot of Panny boards have the equivalent of Q660, it connects VSCN_F to GND for the ramp down portion of the initialisation waveform. If this fails short, but the VFG is stuck HIGH (due to being at that part of the sustain waveform, for example...) this would reverse bias the buffer ICs with 200VDC!!! (As VFG would be at +200VDC, and VSCN_F would be at 0VDC, rather than VFG at +200VDC and VSCN_F at +350VDC.)
This would clearly cause fatal damage to the buffer ICs, AND since the energy path is from VSUS rather than VSCN_F there's a whole lot of energy to dump into the ICs...
As a bonus it would also probably damage the rest of the SC board, due to the pulse energy of discharging the VSCN capacitor...
I have not seen this circuit on modern LG/Samsung sustain boards... only Panasonic.
Just a thought/musing.
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