LG PDP RZ-42PX11 - snow on the dark picture (white is OK)

[Alastair E]

Re: LG PDP RZ-42PX11 - snow on the dark picture (white is OK)

All I can tell you is the F/W file is dated from 2005 (Oldest I have, nothing more recent for a V6 ) and is 4M in size .bin file. What chip its in or in what format/layout/whatever--I have NO idea!

--I would need an email address, as I have no idea what the other options you mention are......

[Gof]

Re: LG PDP RZ-42PX11 - snow on the dark picture (white is OK)

If it's 4MB then it will fit only in the parallel flash, so it must be a firmware for the main CPU. I'm not sure yet what is the simplest way to program it without a jig, but I'll try to find out - there's always an option to unsolder it and program it off-board...

My email is: ohlins@chmurka.net

Thanks!

[Gof]

Re: LG PDP RZ-42PX11 - snow on the dark picture (white is OK)

By the way, where do you connect the jig? To the 12-pin port (P9) called "FPGA_Download"?

[Gof]

Re: LG PDP RZ-42PX11 - snow on the dark picture (white is OK)

Ok, in case someone's interested (maybe someone will find this post looking for the pinout of P9 connector on the web), I've mapped P9 (FPGA_Download) on the control board.

Direction of pins: from left to right.

1. Gnd
2. Gnd
3. Vcc
4. Vcc
5. Flash memory write enable - active low input
6. EPCS1 chip select - active low input, there must be a falling edge after power-up on this pin to begin programming
7. EPCS1 data - data output
8. ? - I couldn't map this pin anywhere...
9. FPGA CONFIG - active low input, falling edge resets FPGA, rising edge begins configuration. All FPGA pins are tristated when this input is low, so I guess it has to be driven low to access other pins without interfering with FPGA
10. EPCS1 ASDI - serial data input
11. FPGA CONF_DONE - I have no idea, datasheet says it's a dedicated configuration status pin, but doesn't say anything more
12. EPCS1 DCLK - clock for DATA and ASDI input (ASDI is latched at the rising edge, data on the DATA pin changes at the falling edge)

Well, it doesn't explain how to program flash memory using this port, only FPGA... if I knew where does the jig connect, it would be easier.

BUT... I found pads for JTAG on the bottom of the board... so it might be possible to do it through them. I'm waiting for the JTAG programmer to arrive (I ordered one from China, so it will take a while), reading about the JTAG (I have no experience with it yet) and I'll try to do it this way (well, first I'll try to read the memory...).

[tom66]

Re: LG PDP RZ-42PX11 - snow on the dark picture (white is OK)

Could be that the JTAG interface chains to the MCM (multi-chip module, the large LG chip, it contains RAM and CPU) which then uses JTAG boundary scan to program the flash.

From some research MCM is made by SHARP Microelectronics, and is a high-speed DSP based on some kind of MIPS architecture. It basically has a large number of serial output drivers for controlling the panel address data and decides what will appear in each display sub-field.

[Gof]

Re: LG PDP RZ-42PX11 - snow on the dark picture (white is OK)

Yeah, it should be possible to program it with boundary scan, first discovering how the memory pins are connected to the MCM pins.

I have zero experience with JTAG yet, but I'm reading urjtag manual:

http://urjtag.org/book/_jtag_commands.html

There are two commands that look promising: discovery and detectflash.

It doesn't seem to support this flash and it supports only one Sharp MCU... but I'll give it a try when the JTAG programmer arrives...

[Gof]

Re: LG PDP RZ-42PX11 - snow on the dark picture (white is OK)

I'm happy to bump this thread to say that the problem is mostly fixed. Control board was good (no fw upgrade was needed), but ysus board was faulty. I don't know what failed exactly, but it wasn't the IPM, as I checked it.

Anyway, I replaced the ysus, regulated voltages and two ramps on it and it seems almost ok. I regulated voltages according to the sticker on the panel, not to voltages in service manual, which were different, for example -Vy on panel was -70V and in service manual -75V.

The picture is clear, but there are rare green hotpixels on certain areas of the picture (it seems to depend of the luminance in that area), I hope that decreasing Vs will help (but I didn't try it yet).

I have however a problem with regulating zsus signal width with VR3 on zsus board. Turning VR3 does not produce any changes on the signal, as observed on the oscilloscope. There are also no visible changes on the screen, regardless of displayed picture (I tried with 100% white and with an actual picture).

Could it indicate zsus failure, too, or is the regulation very suble, or something?