Re: Plasma Pixelization SAMSUNG PS50B430
Yes I have a scope. Wich waveform must be present? I have checked all the igbt, mosfet and diodes present on the heatsink one by one. All are OK
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Re: Plasma Pixelization SAMSUNG PS50B430
The software update was my first step the software is the latest version.
I attemp to up Vs but no change.
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Re: Plasma Pixelization SAMSUNG PS50B430
Vsc is OK ! I have reflow all the joints on The Ysus.
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Re: Plasma Pixelization SAMSUNG PS50B430
Yes ERC for the energy recovery circuit!
Do you think the panel may be faulty? Because a trace remains very quickly if I consult the menu for example but the trace disappears after.Last edited by creatou; 11-24-2016, 09:45 AM.
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Re: Plasma Pixelization SAMSUNG PS50B430
As I said I remade all the welds. the photo are before! Ve is OK. What is ERC default
Many thanks for your helpLast edited by creatou; 11-23-2016, 01:34 PM.
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Re: Plasma Pixelization SAMSUNG PS50B430
Here is the Xmain board solder side in two part. I have reflow all the joint and test ! no change idem with the Ymain....
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Re: Plasma Pixelization SAMSUNG PS50B430
VE is 89V
Can you said me witch is the number of the board you name Xmain (see picture )
Thank's
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Re: Plasma Pixelization SAMSUNG PS50B430
Can you confirm the position of the boad on the attached image for my unit.
1: Ysus
2: Zsus
3: Xlogic driver
4: Logic board
5: main boaord
6: PSU
Which board appears to be in default?
ReeceyBurger123 said "Xmain"...
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Re: Plasma Pixelization SAMSUNG PS50B430
I make a picture as soon as possible. The picture was just to show the Xsus card model
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Re: Plasma Pixelization SAMSUNG PS50B430
hi,
Thank's for your reply.
I checked the welding on Xmain especially on the large inductors but nothing abnormal.
I'll check again this evening....
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Plasma Pixelization SAMSUNG PS50B430
Hello everyone
I would like the opinion of plasma experts. Attached is the picture of a Samsung PS50B430 50 "Plasma TV during test pattern in service mode. The image is polished by pixels that sparkle mostly on the green and blue.
My voltages VS, Va, Ve, Vscan, Vcc, Vdd are correct.
I unplugged the LVDS from the logic main board and switched it to test mode (shunt pin 3 and 4). The black snow is always present on all the pattern of test. I can eliminate the hand board is already that
Do you have any idea of the cause of this defect.
Thank...
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