There IS a clear 1.8V data/clock burst from the T2 right at power-on.
This confirms the T2 is executing its initial sequence and sending the SPMI command to U7800. However, U7800 still fails to output/sustain PP3V3_S5.
Since T2 communication is verified present, what hardware condition, PWR_GOOD, or internal PMIC trigger line should I trace next on U7800 that could prevent it from executing the S5 turn-on request?...
Leave a comment: