Samsung UE32D6515WS — boot loop + what does this pixel pattern suggest?

[ohren]

I'm trying to determine the nature of these faults and whether they're coincidental or in fact connected.

Symptom 1: boot looping, showing logo and then going blank, backlight turning on for 2 s or 14 s intermittently, and arriving at logo again after approx 1 minute. Never appears to boot fully.

Symptom 2: vertical lines across whole screen while logo showing. Every 4th pixel column.

Backlight seems to work fine and is lit while logic board is disconnected. 12v, 5V seem stable and only dip when the system resets.

System still seems to reboot when T-con board is disconnected. Same when LCD disconnected.

Everything on the boards looks more or less pristine. I can't pinpoint it more than it's either the logic or T-con board.

I do repairs for fun, i.e. I'm always interested in early opinions on whether the fault is likely to be extremely tedious or needlessly expensive to troubleshoot.

[ohren]

Is there any additional info I can provide to help someone lend their intuition about the pattern?

Here are some clues:

• The visual artifacts occur on every fourth pixel column
• They seem to always occur on the same columns between reboots
• They occur over the boot image
• The boot image seem to affect the appearance of the artifacts (what looks like the image's bounds become discernible — imperfect black background color in interplay with the fault?), i.e. what the picture is supposed to look like seems to have an effect on the artifacts
• The artifacts differ between reboots
• The artifacts are static each boot and do not flicker in the few seconds they're visible

My conclusions:

• The artifacts are stored in some frame buffer since they are stable and don't flicker
• They occur before they're sent to the t-con board
• They're somehow connected with the CPU or with the component responsible for feeding the t-con board

Since I'm not that familiar with TV architectures my assumptions are:

• The display of initial boot images are not handled by the t-con board, but by the logic board
• The logic board feeds the t-con board a fixed number of frames per second (I.e. everything beyond the logic board is basically fixed frame rate signals)

Does anyone have a hunch? Are my assumptions wrong? Is it futile to reason about faults like these in this way? I'm happy just learning how to decide where to put my focus.