P5B-plus d3-d7 post code

[Morsus]

Hello,
I got an Asus P5B-PLUS motherboard witch wont give me picture. The CPU fan is working, the led on board is on but the picture on screen never shows up. Graphic card works 100%.
When I inserted pc analyzer it gave me these codes:
D3D3 without any RAM memories,
D7D7 with RAM memories (in all slots, few different modules,together or solo).

AMI (D3)DMA controller #1,#2,interrupt controller #1,#2 disable. Video display is
disable and port-B is initialized. Chipset initialize/auto memory detection about to
begin.

another PC analyzer code book

Starting memory sizing next.

None of these have any information on D7D7 error code. Any help will be appreciated. Thank you!

[ChaosLegionnaire]

Re: P5B-plus d3-d7 post code

this type of error typically indicates ram or memory controller issues. usually, u'd check for bad caps around the dimm slots and then check the voltage regulator for the ram. then the northbridge. maybe northbridge needs a reflow or the mosfet powering the northbridge went bad.

[Morsus]

Re: P5B-plus d3-d7 post code

Checked the fets, they seem fine. I replaced the two caps near DIMM slots, same result. Reflowed the northbridge - same results. After replacing one of two caps near northbridge pc analyzer outputed 4040 error.

Preparing the descriptor tables next.

Preparation for virtual mode test started. Going to verify from video memory.
CACHE memory on and about to disable A20 address line.

I'm guessing this is a step back... :/

[ChaosLegionnaire]

Re: P5B-plus d3-d7 post code

actually, its fine. for modern ami bios (i'm assuming this since its an asus board) based boards post-2002, its starts with the D post codes which is early chipset and ram, bootblock and bios flash initialisation. btw, the d7 post code means:

D7 - Restore CPUID value back into register. The Bootblock-Runtime interface module is moved to system memory and control is given to it. Determine whether to execute serial flash.

now u made it all the way to post checkpoint 40, which is almost there to mid-late post, so its an improvement. post code 40 means this:

40 - Detect different devices (Parallel ports, serial ports, and coprocessor in CPU, … etc.) successfully installed in the system and update the BDA, EBDA…etc.

this may indicate a mobo onboard device has failed and could be holding up the boot/post process. u have to find out which one is the culprit. note: it is possible for more than one onboard device to be bad and holding up the post process.

btw, most post code booklets that come with post analyzer cards have obsolete info in them that pertain only to pentium pro, 486 or earlier bios. for 2002 or later pentium 4 or athlon xp boards, the post code booklets shouldnt be trusted. i have a post card and the post code booklet that came with it wasnt helpful at all for troubleshooting the modern boards i had.

[Morsus]

Re: P5B-plus d3-d7 post code

Thank you, all this info is much appreciated. Can you give me an idea on how to find the culprit? I'm guessing looking for heated components, maybe alcohol trick.

Do you have better table of bios post codes I could use?

[Morsus]

Re: P5B-plus d3-d7 post code

Sorry for double posting :/
I'm reading what northbridge controls (communication between CPU,GPU slot (AGP or PCI-E)) and RAM. Could it be that I fixed the northbridge but in the same time broke RAM? Since I used not so exact cap to replace original ones.

[Morsus]

Re: P5B-plus d3-d7 post code

Another update:

I have just returned the 470uF 6.3V (witch I replaced with 470uF 16V before) back to the board. And now my analyzer displays an 6060 error code.

Code 6060:

The DMA page register test passed. Performing the DMA Controler 1 base registar test next.

DMA page register test passed. About to go for DMA #1,verify from display
memory.

At this point I tried to power it with graphic card witch gave me 6F6F error code. And playing with RAM modules and another graphic card result me in error codes 9898 and for the first time D4D4.

Code D4D4:

Uncompressed RUNTIME code.
Chipset Initialization/auto memory detection about to begin. Check SIMM for
mismatch.
Returning to real mode. Executing any OEM patches and setting the stack next.

Code 9898:

Clear all Interrupts.
All Interupts cleared.
Control to optional ROM
Optional ROM control is done. About to give control to do any required
processing after optional ROM returns control.

No info on AMI 6F6F code.

[ChaosLegionnaire]

Re: P5B-plus d3-d7 post code

ok well here is the full listing of ami bios rev8 post codes. i got it from the postcodemaster.com website but it appears to have gone down recently. guess the owner forgot to pay the bill... anyway...

AMI BIOS Rev 8 AMIBIOS8 10/01/2002 BIOS POST Codes 

Before D1 - Early chipset initialization is done. Early super I/O initialization is done including RTC and keyboard controller. NMI is disabled.
D1 - Perform keyboard controller BAT test. Check if waking up from power management suspend state. Save power-on CPUID value in scratch CMOS.
D0 - Go to flat mode with 4GB limit and GA20 enabled. Verify the bootblock checksum.
D2 - Disable CACHE before memory detection. Execute full memory sizing module. Verify that flat mode is enabled.
D3 - If memory sizing module not executed, start memory refresh and do memory sizing in Bootblock code. Do additional chipset initialization. Re-enable CACHE. Verify that flat mode is enabled.
D4 - Test base 512KB memory. Adjust policies and cache first 8MB. Set stack.
D5 - Bootblock code is copied from ROM to lower system memory and control is given to it. BIOS now executes out of RAM.
D6 - Both key sequence and OEM specific method is checked to determine if BIOS recovery is forced. Main BIOS checksum is tested. If BIOS recovery is necessary, control flows to checkpoint E0. See Bootblock Recovery Code Checkpoints section of document for more information.
D7 - Restore CPUID value back into register. The Bootblock-Runtime interface module is moved to system memory and control is given to it. Determine whether to execute serial flash.
D8 - The Runtime module is uncompressed into memory. CPUID information is stored in memory.
D9 - Store the Uncompressed pointer for future use in PMM. Copying Main BIOS into memory. Leaves all RAM below 1MB Read-Write including E000 and F000 shadow areas but closing SMRAM.
DA - Restore CPUID value back into register. Give control to BIOS POST (ExecutePOSTKernel). See POST Code Checkpoints section of document for more information.
E0 - Initialize the floppy controller in the super I/O. Some interrupt vectors are initialized. DMA controller is initialized. 8259 interrupt controller is initialized. L1 cache is enabled.
E9 - Set up floppy controller and data. Attempt to read from floppy.
EA - Enable ATAPI hardware. Attempt to read from ARMD and ATAPI CDROM.
EB - Disable ATAPI hardware. Jump back to checkpoint E9.
EF - Read error occurred on media. Jump back to checkpoint EB.
E9 or EA - Determine information about root directory of recovery media.
F0 - Search for pre-defined recovery file name in root directory.
F1 - Recovery file not found.
F2 - Start reading FAT table and analyze FAT to find the clusters occupied by the recovery file.
F3 - Start reading the recovery file cluster by cluster.
F5 - Disable L1 cache.
FA - Check the validity of the recovery file configuration to the current configuration of the flash part.
FB - Make flash write enabled through chipset and OEM specific method. Detect proper flash part. Verify that the found flash part size equals the recovery file size.
F4 - The recovery file size does not equal the found flash part size.
FC - Erase the flash part.
FD - Program the flash part.
FF - The flash has been updated successfully. Make flash write disabled. Disable ATAPI hardware. Restore CPUID value back into register. Give control to F000 ROM at F000:FFF0h.
03 - Disable NMI, Parity, video for EGA, and DMA controllers. Initialize BIOS, POST, Runtime data area. Also initialize BIOS modules on POST entry and GPNV area. Initialized CMOS as mentioned in the Kernel Variable "wCMOSFlags."
04 - Check CMOS diagnostic byte to determine if battery power is OK and CMOS checksum is OK. Verify CMOS checksum manually by reading storage area. If the CMOS checksum is bad, update CMOS with power-on default values and clear passwords. Initialize status register A. Initializes data variables that are based on CMOS setup questions. Initializes both the 8259 compatible PICs in the system
05 - Initializes the interrupt controlling hardware (generally PIC) and interrupt vector table. 
06 - Do R/W test to CH-2 count reg. Initialize CH-0 as system timer. Install the POSTINT1Ch handler. Enable IRQ-0 in PIC for system timer interrupt. Traps INT1Ch vector to "POSTINT1ChHandlerBlock." 
08 - Initializes the CPU. The BAT test is being done on KBC. Program the keyboard controller command byte is being done after Auto detection of KB/MS using AMI KB-5. 
C0 - Early CPU Init Start -- Disable Cache - Init Local APIC
C1 - Set up boot strap proccessor Information
C2 - Set up boot strap proccessor for POST 
C5 - Enumerate and set up application proccessors
C6 - Re-enable cache for boot strap proccessor
C7 - Early CPU Init Exit 
0A - Initializes the 8042 compatible Key Board Controller. 
0B - Detects the presence of PS/2 mouse. 
0C - Detects the presence of Keyboard in KBC port. 
0E - Testing and initialization of different Input Devices. Also, update the Kernel Variables. Traps the INT09h vector, so that the POST INT09h handler gets control for IRQ1. Uncompress all available language, BIOS logo, and Silent logo modules.
13 - Early POST initialization of chipset registers. 
24 - Uncompress and initialize any platform specific BIOS modules. 
30 - Initialize System Management Interrupt. 
2A - Initializes different devices through DIM. See DIM Code Checkpoints section of document for more information.
2C - Initializes different devices. Detects and initializes the video adapter installed in the system that have optional ROMs.
2E - Initializes all the output devices. 
31 - Allocate memory for ADM module and uncompress it. Give control to ADM module for initialization. Initialize language and font modules for ADM. Activate ADM module.
33 - Initializes the silent boot module. Set the window for displaying text information. 
37 - Displaying sign-on message, CPU information, setup key message, and any OEM specific information.
38 - Initializes different devices through DIM. See DIM Code Checkpoints section of document for more information. 
39 - Initializes DMAC-1 & DMAC-2. 
3A - Initialize RTC date/time. 
3B - Test for total memory installed in the system. Also, Check for DEL or ESC keys to limit memory test. Display total memory in the system. 
3C - Mid POST initialization of chipset registers. 
40 - Detect different devices (Parallel ports, serial ports, and coprocessor in CPU, … etc.) successfully installed in the system and update the BDA, EBDA…etc. 
50 - Programming the memory hole or any kind of implementation that needs an adjustment in system RAM size if needed. 
52 - Updates CMOS memory size from memory found in memory test. Allocates memory for Extended BIOS Data Area from base memory. 
60 - Initializes NUM-LOCK status and programs the KBD typematic rate. 
75 - Initialize Int-13 and prepare for IPL detection. 
78 - Initializes IPL devices controlled by BIOS and option ROMs. 
7A - Initializes remaining option ROMs.
7C - Generate and write contents of ESCD in NVRam. 
84 - Log errors encountered during POST. 
85 - Display errors to the user and gets the user response for error. 
87 - Execute BIOS setup if needed / requested. 
8C - Late POST initialization of chipset registers. 
8D - Build ACPI tables (if ACPI is supported) 
8E - Program the peripheral parameters. Enable/Disable NMI as selected 
90 - Late POST initialization of system management interrupt.

ooops need to split my post due to 10k char limit... TBC in next post.

[ChaosLegionnaire]

Re: P5B-plus d3-d7 post code

A0 - Check boot password if installed. 
A1 - Clean-up work needed before booting to OS. 
A2 - Takes care of runtime image preparation for different BIOS modules. Fill the free area in F000h segment with 0FFh. Initializes the Microsoft IRQ Routing Table. Prepares the runtime language module. Disables the system configuration display if needed. 
A4 - Initialize runtime language module. 
A7 - Displays the system configuration screen if enabled. Initialize the CPU's before boot, which includes the programming of the MTRR's. 
A8 - Prepare CPU for OS boot including final MTRR values. 
A9 - Wait for user input at config display if needed. 
AA - Uninstall POST INT1Ch vector and INT09h vector. Deinitializes the ADM module.
AB - Prepare BBS for Int 19 boot. 
AC - End of POST initialization of chipset registers.
B1 - Save system context for ACPI.
00 - Passes control to OS Loader (typically INT19h). 
2A - Initialize different buses and perform the following functions: Reset, Detect, and Disable (function 0); Static Device Initialization (function 1); Boot Output Device Initialization (function 2). Function 0 disables all device nodes, PCI devices, and PnP ISA cards. It also assigns PCI bus numbers. Function 1 initializes all static devices that include manual configured onboard peripherals, memory and I/O decode windows in PCI-PCI bridges, and noncompliant PCI devices. Static resources are also reserved. Function 2 searches for and initializes any PnP, PCI, or AGP video devices.
38 - Initialize different buses and perform the following functions: Boot Input Device Initialization (function 3); IPL Device Initialization (function 4); General Device Initialization (function 5). Function 3 searches for and configures PCI input devices and detects if system has standard keyboard controller. Function 4 searches for and configures all PnP and PCI boot devices. Function 5 configures all onboard peripherals that are set to an automatic configuration and configures all remaining PnP and PCI devices.
While control is in the different functions, additional checkpoints are output to port 80h as a word value to identify the routines under execution. The low byte value indicates the main POST Code Checkpoint. The high byte is divided into two nibbles and contains two fields. The details of the high byte of these checkpoints are as follows: 
HIGH BYTE XY 
The upper nibble 'X' indicates the function number that is being executed. 'X' can be from 0 to 7. 
0 = func#0, disable all devices on the BUS concerned. 
1 = func#1, static devices initialization on the BUS concerned. 
2 = func#2, output device initialization on the BUS concerned. 
3 = func#3, input device initialization on the BUS concerned. 
4 = func#4, IPL device initialization on the BUS concerned. 
5 = func#5, general device initialization on the BUS concerned. 
6 = func#6, error reporting for the BUS concerned. 
7 = func#7, add-on ROM initialization for all BUSes. 
8 = func#8, BBS ROM initialization for all BUSes. 
The lower nibble 'Y' indicates the BUS on which the different routines are being executed. 'Y' can be from 0 to 5. 
0 = Generic DIM (Device Initialization Manager). 
1 = On-board System devices. 
2 = ISA devices. 
3 = EISA devices. 
4 = ISA PnP devices. 
5 = PCI devices. 
AC - First ASL check point. Indicates the system is running in ACPI mode. 
AA - System is running in APIC mode. 
01, 02, 03, 04, 05 - Entering sleep state S1, S2, S3, S4, or S5. 
10, 20, 30, 40, 50 - Waking from sleep state S1, S2, S3, S4, or S5.

anyway, codes 60 and 98 are almost to late post just barely before it displays stuff on the screen. code d4 is back in early post and is testing base 512k ram (ram initialisation) and is a major step back. have u tried reflowing the southbridge too? maybe it needs a reflow as well seeing how something onboard is holding up the post. if post is successful, it should display the 3738 post code when it is able to display bios boot/post messages on screen.

[Morsus]

Re: P5B-plus d3-d7 post code

Thank you a lot.
I reflowed the southbridge too after witch I got an 4040 post code back. After that I replaced that one cap next to northbridge again. And now the analyzer gives 1010 to me.
In your tables it says "Waking up from sleep state". Im guessing its stuck in sleep so it does not turn on or something like that. I tried clearing the bios but no luck.

Any ideas?

[ChaosLegionnaire]

Re: P5B-plus d3-d7 post code

this board looks like it has been damaged by too much ripple from a junk power supply. did u get the whole system or board only? see if u can confirm if a junk/unknown brand psu was used? if so, make sure u use a good quality branded power supply. unstable power can cause issues like that.

i recommend replacing all the caps around the nb/sb/dimms and cpu. the flash memory in the bios chip can also be bad and start losing its contents if the power supplied to the chip was unstable. either swap to a new bios chip or reflash the bios chip with a serial flash programmer.